Integrated circuits are becoming more dense as the dimensions of semiconductor devices decrease. The decreased dimensions also provide for faster devices that require less power to operate. In particular, present generation semiconductor devices, such as transistors, operate on less voltage (.about.3.3V) than the previous generation voltage (5V). One benefit of having lower operating voltage, and consequently lower power consumption, is that demands on the power supply is decreased. This is especially important where the portability of an electronic device incorporating these semiconductor devices is desired. The power supply, such as a battery, can be smaller or would last longer.
Many electronic devices and components, however, still incorporate integrated circuits consisting of semiconductor devices that use a higher voltage (5V). Thus, applications may arise where both low and high voltage integrated circuits are connected together. An integrated circuit operating on a lower voltage must then to receive an input at the higher voltage. However, the structural integrity of the thin film oxide will suffer if exposed to voltage potentials in excess of the maximum rated supply, typically 3.6V to 4.0V. A 5 volt drop from the gate to the drain, source or substrate will tend to breakdown this oxide. A long-term reliability issue will result, with the oxide breakdown eventually causing catastrophic damage to the transistor.
Referring to FIG. 1, an input buffer 100 is illustrated. A lead 105 couples an input pad (not shown) to an n-channel transistor 110. A gate of n-channel transistor 110 is coupled to a voltage supply (not shown) via a lead 115. A substrate of n-channel transistor 110 is coupled to a reference supply (not shown) via a lead 120.
A node 125 is coupled to gates of a p-channel transistor 130 and an n-channel transistor 135. A source and a substrate of p-channel transistor 130 is coupled via a lead 140 to the voltage supply. A source and a substrate of n-channel transistor 135 is coupled via a lead 145 to the reference supply. A node 150 is coupled to drains of p-channel transistor 130 and n-channel transistor 135. Node 150 is coupled to a circuit (not shown) via a lead 155.
For input buffer 100 in a 0.5 .mu.m process technology, assume that threshold voltage for p-channel transistor 130 is about -0.9V and the voltage supply provides 3.3V. By using n-channel transistor 110, the voltage at node 125 will have a maximum voltage swing that ranges from 0V to about 2.8V as the input pad voltage transitions from 0V to 5V. The voltage at node 125 reaches 2.8V due to the body effect of n-channel transistor 110. P-channel transistor 130 is prevented from conducting since its gate voltage is greater than its source voltage minus its threshold voltage (2.8&gt;3.3-0.9). Thus, static power is not dissipated through the stack consisting of p-channel transistor 130 and n-channel transistor 135.
The body effect causes the threshold voltage of a transistor to increase as the source to substrate voltage increases for an n-channel transistor and decrease for a p-channel device. Body effect is roughly constant over different processing technologies.
For input buffer 100 in a 0.35 .mu.m process technology, assume that threshold voltage for p-channel transistor 130 is about -0.6V. The voltage at node 125 will have a maximum voltage swing that ranges from 0V to about 2.7V as the input pad voltage transitions from 0V to 5V. The voltage at node 125 reaches 2.7V due to the body effect of n-channel transistor 110. Unlike the 0.5.mu.m technology example, p-channel transistor 130 conducts since its gate voltage is about the same as the source voltage minus its threshold voltage (2.7.about.3.3-0.6). Thus, static power is dissipated through the stack consisting of p-channel transistor 130 and n-channel transistor 135. Furthermore, since buffer 100 typically has large device sizes, the static current dissipated through the stacked transistors can be substantial.
Other devices compensate for this dissipated static current. However, these devices unfortunately cause contention with the input voltage so that a high impedance input is not achieved. Such a high impedance is a requirement for CMOS input buffers.
There exists, then, a need for an input buffer that can receive a high voltage input and yet dissipate low power. This buffer will also provide a high impedance input. The present invention meets this need.